1. Field of the Invention
This invention relates generally to computer systems and more particularly to a generic asynchronous bus interface capable of communicating with a variety of microprocessors.
2. Description of the Related Art
Portable consumer electronic devices are pervasive in all aspects of society today. Examples of such devices include personal digital assistants (PDA), mobile phones, pagers, web tablets, etc. These portable devices contain embedded systems that include central processing units (CPU). Due to the narrow range of functions provided by these handheld devices, the CPUs associated with these embedded systems are not required to have as powerful computing power as desktop or laptop CPUs. A number of vendors provide CPUs designed specifically for a type of handheld device. As is well known, the CPUs also include native buses that support the CPUs. Additionally, the devices include a display screen where images are presented under the control of a display controller, such as a liquid crystal display (LCD) controller. The display controller, typically manufactured by a vendor different from the CPU vendor, is customized to include a bus interface that allows the display controller to communicate with specific CPUs through a system bus. Because of the wide variety of the CPUs, the display controllers tend to be customized to interface with a narrow range of CPUs.
Additionally, the various CPUs and the display controllers available on the market can run at different clock speeds. Thus, the data bus through which the CPU and the LCD controller communicate, may be asynchronous to accommodate the different speeds at which the CPU and LCD controller operate. That is, since events do not happen at predetermined times, as would be the case if the CPU and the LCD controller were using the same clocks, the bus interface accommodates interlocked communication, also referred to as handshaking. Moreover, for power save purposes the display controllers targeted for specific CPUs switch to an external crystal to provide the clock. However, the external crystal may be running at a fraction of the frequency of the nominal bus frequency. Thus, certain limitations on the difference between clock speeds have to be put in place in order for the CPU and the display controller to communicate. Furthermore, it should be appreciated that the term “asynchronous” is applied loosely to bus interfaces that include a WAIT signal to allow for a variable length access. If the bas interface allows variable length access through a WAIT signal and the bus master and the bus slave use the same bus clock, i.e., define all bus events relative to a bus clock signal, then the bus interface is not truly asynchronous since the timing is slaved to a single CPU oscillator. Different clocks are used to drive and sample signals under a truly asynchronous bus interface.
FIG. 1 is a schematic diagram of an embedded system including a CPU in communication with a display controller, such as a LCD controller. CPU 100 communicates through bus 102 to bus interface 104 of LCD controller 106. CPU 100 is configured to run at speed Y while LCD controller 106 is configured to run at speed X. The different clock speeds of CPU 100 and LCD controller 106 cause issues when there is a large difference between the two clock speeds. The situation where LCD controller 106 runs at a clock speed of 1 Kilohertz (KHz) and CPU 100 runs at a clock speed of 100 Megahertz (MHz) is considered for exemplary purposes. Under these conditions, CPU 100 asserts a signal over a clock period that is a 100 MHz clock period. LCD controller 106, running at 1 KHz, is unlikely to be able to sample the asserted signal during the allotted clock period because of the discrepancy in clock speeds. Thus, LCD controller 106 will be unable to communicate with CPU 100.
One approach to address the issues caused by the different operating speeds is to set a limit for a difference between the speeds of the LCD controller and the CPU. That is, the LCD controller is targeted for CPUs having particular clock speeds based upon the clock speed difference between the LCD controller and the CPU. In addition, the LCD controller will double or triple sample a signal to guarantee within a certain time period that the signal will be sampled in order to compensate for the speed differences. That is, repeating the sampling of the signal when the speeds of the controllers are within a certain range will guarantee that the signal is sampled within the allotted clock period. One limitation of this approach is that the CPU and the LCD controller must be within a certain speed range of each other or this approach to operating in an asynchronous mode will not work.
Furthermore, because the CPU asserts signals on a different clock from the clock used by the LCD controller to receive the signals, an asynchronous bus interface can encounter a metastable condition. A flip flop or latch circuit within the bus interface of the LCD controller that receives a signal generated from the CPU has a setup and a hold time associated with the D input to the flip flop. If the setup or hold time of the flip flop is violated, then the output (Q) could become metastable. That is, the flip flop becomes “confused” to which state to go into when the rising edge of the clock for the LCD controller occurs at the same time that the CPU asserts the signal, thereby providing two infinite slopes on a signal. Since the clock for the flip flop is the LCD clock, which is separate from the clock used by the CPU to generate the signals, it can not be guaranteed that input transitions do not occur during setup intervals. The metastable condition is disastrous for a chip, since the bus cycle will fail. Thus, the occurrence of metastable conditions must be minimized in order for an asynchronous bus interface to reliably operate.
As a result, there is a need to solve the problems of the prior art to provide a display controller with an asynchronous generic bus interface capable of communicating with a variety of microprocessors irrespective of the difference in operating speeds between the display controller and the microprocessor. Additionally the circuitry of the display controller should be configured to minimize the occurrence of a metastable condition.